This invention relates to MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and more particularly to fabrication of a wide metal silicide on a narrow polysilicon gate structure of a MOSFET for a gate with low series resistance in MOSFETs with scaled down dimensions.
Referring to FIG. 1, a cross sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 includes a drain region 102, a source region 104, and a channel region 106 fabricated on an insulating layer 107 disposed over a semiconductor substrate 108 for SOI (silicon-on-insulator) technology, as known to one of ordinary skill in the art of electronics. A gate dielectric 110 is disposed over the channel region 106 of the MOSFET 100. The MOSFET 100 also includes a gate comprised of a polysilicon structure 112 disposed over the gate dielectric 110. Spacer structures 113 typically formed of an insulating material surround the gate dielectric 110 and the polysilicon structure 112, as known to one of ordinary skill in the art of electronics. Isolation dielectric structures 120 electrically isolate the MOSFET 100 from other devices fabricated on the insulating layer 107.
For making contact to the drain region 102, the source region 104, and the polysilicon structure 112 of the gate, a metal silicide is formed on the drain region 102, the source region 104, and the polysilicon structure 112 of the gate. A drain silicide 114 is formed on the drain region 102, a source silicide 116 is formed on the source region 104, and a gate silicide 118 is formed on the polysilicon structure 112 of the gate of the MOSFET 100.
For efficiency in fabrication, the drain silicide 114, the source silicide 116, and the gate silicide 118 are typically fabricated simultaneously in the prior art. During the fabrication of the suicides, the drain region 102, the source region 104, and the polysilicon structure 112 are exposed, and metal is deposited on those regions. Then, a silicidation anneal is performed, and the drain silicide 114, the source silicide 116, and the gate silicide 118 form from a reaction of the deposited metal with silicon during the silicidation anneal. Thus, in the prior art, the drain silicide 114, the source silicide 116, and the gate silicide 118 have substantially the same thickness and is comprised of substantially the same metal silicide material.
However, as structures of the MOSFET are modified with advancement in technology, it may be desired that the thickness of the drain silicide 114 and the source silicide 116 be different from the thickness of the gate silicide 118. In addition, it may be desired that the metal silicide material for the drain silicide 114 and the source silicide 116 be different from the metal silicide material of the gate silicide 118.
For example, a long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is to enhance the speed performance of the integrated circuit. Thus, the MOSFET 100 is fabricated with SOI (silicon-on-insulator) technology whereby the drain region 102, the source region 104, and the channel region 106 are fabricated on the insulating layer 107 to eliminate junction capacitance, as known to one of ordinary skill in the art of electronics. Because the drain region 102 and the source region 104 are fabricated directly on the insulating layer 107, the depth of the drain region 102 and the source region 104 may be limited. In that case, the thickness of the drain silicide 114 and the source silicide 116 in turn are limited. On the other hand, a large thickness of the gate silicide 118 is desired for minimizing the resistance at the gate of the MOSFET and in turn for maximizing the speed performance of the MOSFET.
In addition, another long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, as the dimensions of the MOSFET 100 are scaled down, a smaller thickness is desired for the drain silicide 114 and the source silicide 116 to minimize small channel effects of the MOSFET, as known to one of ordinary skill in the art. On the other hand, a large thickness of the gate silicide 118 is desired for minimizing the resistance at the gate of the MOSFET and in turn for maximizing the speed performance of the MOSFET.
Some metal silicides, such as nickel silicide (NiSi2), are more amenable for forming a thin metal silicide. Thus, it may be desired that the drain silicide 114 and the source silicide 116 be comprised of nickel silicide (NiSi2). Other metal suicides, such as cobalt silicide (CoSi2) or titanium silicide (TiSi2), are more amenable for forming a thick metal silicide. Thus, it may be desired that the gate silicide 118 be comprised of cobalt silicide (CoSi2) or titanium silicide (TiSi2) while the drain silicide 114 and the source silicide 116 may be comprised of nickel silicide (NiSi2) such that the gate silicide 118 is comprised of a different metal silicide material from that of the drain silicide 114 and the source silicide 116.
Furthermore, with scaling down of the dimensions of the polysilicon structure 112 of the MOSFET, the volume of the gate silicide 118 is also scaled down resulting in higher series resistance at the gate of the MOSFET 100. Such higher series resistance degrades the speed performance of the MOSFET.
Thus, a gate silicide is desired to have a larger thickness than that of the drain silicide and the source silicide, and to be comprised of a metal silicide material that may be different from that for the drain silicide and the source silicide. In addition, a gate silicide is desired to have a larger width than that of the narrow polysilicon gate structure in a MOSFET with scaled down dimensions.
Accordingly, the present invention is directed to a separate step for fabrication of the gate silicide from the step for fabrication of the drain silicide and the source silicide such that the gate silicide may have a different thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide. In addition, additional polysilicon material is added to the polysilicon gate for fabrication of a gate silicide having a larger width that the width of the narrow polysilicon gate structure in a MOSFET with scaled down dimensions.
Accordingly, in a general aspect of the present invention, a MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon structure disposed on a gate dielectric over the channel region. A drain silicide and a source silicide having a first silicide thickness are formed in the drain region and the source region, respectively, of the MOSFET. A dielectric layer is deposited over the drain region, the source region, and the gate. The dielectric layer is polished down over the drain region, the source region, and the gate until the capping layer of the gate is exposed such that the capping layer and the dielectric layer are substantially level. The capping layer on the polysilicon structure of the gate is etched away such that the top of the polysilicon structure is exposed. A top portion of the dielectric layer is etched away until sidewalls at a top portion of the polysilicon structure are exposed. A polysilicon spacer is formed at the exposed sidewalls at the top portion of the polysilicon structure. A silicidation metal is deposited on the top of the polysilicon structure that is exposed and on the polysilicon spacer. A silicidation anneal is performed with the silicidation metal and the polysilicon structure that is exposed and the polysilicon spacer to form a gate silicide having a second silicide thickness on top of the polysilicon structure of the gate.
In this manner, because the gate silicide is formed with the added polysilicon spacer at the exposed sidewalls of the polysilicon structure, the gate silicide has a width that is larger than the width of the polysilicon structure of the gate. In addition, the gate silicide is formed in a separate step from the step of forming the drain silicide and the source silicide such that the gate silicide may have a larger thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide. The larger width and the larger thickness of the gate silicide results in minimized resistance at the gate of the MOSFET for enhanced speed performance of the MOSFET.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.